
Watlow EZ-ZONE
®
RM A M odule • 69 • Cha pter 8 A ppendix
Assembly
Class,
Instance,
Module
Availabilty
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Assembly
Instance,
Attribute
Module
Availabilty
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Assembly
Class,
Instance,
Module
Availabilty
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Assembly
Class,
Instance,
Module
Availabilty
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Limt Loop
O2T
(C) 0x71 (113)
(I) 1 to 24
(A) 0x0A (10)
RML spare
Limit
clear
Clear
latched
error
Assembly
Instance,
Module
Availabilty
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Limit Loop
O2T
(C) 0x71 (113)
(I) 1 to 24
(A) 7
RML spare
Limit
clear
Clear
latched
error
Assembly
Class,
Instance,
Attribute
Module
Availabilty
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RML spare
Limit
clear
spare
Limit
clear
spare
Limit
clear
spare
Limit
clear
spare
Limit
clear
spare
Limit
clear
spare
Limit
clear
spare
Limit
clear
Assembly
Class,
Instance,
Module
Availabilty
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Alarm
clear
Alarm
silence
Alarm
clear
Alarm
silence
Alarm
clear
Alarm
silence
Alarm
clear
Alarm
silence
Alarm
clear
Alarm
silence
Alarm
clear
Alarm
silence
Alarm
clear
Alarm
silence
Alarm
clear
Alarm
silence
Assembly
Instance,
Module
Availabilty
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Alarm
clear
Assembly
Instance,
Attribute
Module
Availabilty
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Assembly
Class,
Instance,
Attribute
Module
Availabilty
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bits 16, 18, 20, 22, 24, 26, 28 and 30, Limit Clear for instance i to instance i + 15 respectively (0 =
Ignore, 1 = Clear)
Bits 16, 18, 20, 22, 24, 26, 28 and 30, Alarm Silence for instance i to instance i + 15
respectively (0 = Ignore, 1 = Clear)
Bits 17, 19, 21, 23, 25, 27, 29 and 31, Alarm Clear for instance i to instance
i + 15 respectively (0 = Ignore, 1 = Silence)
Alarm O2T
(C) 0x71 (113)
(I) 1 to 24
(A) 0x0D (13)
Digital State Digital State Digital State Digital State
Variable O2T
(C) 0x71 (113)
(I) 1 to 24
(A) 4
RMH
(C) 0x71 (113)
(I) 1 to 24
RMH
Control Loop
O2T
Closed Loop Set Point (instance i +1)
RMH
RML
RMS
RMH
RML
RMS
Analog Value
Bit 30, Clear Latched Error (0 = Ignore, 1 = Clear)
Limit Set Point High (instance i)
Bit 29, Clear Latched Input Error (0 = Ignore, 1 = Clear)
(C) 0x71 (113)
(I) 1 to 24
(A) 0x0E (14)
Limt Loop
O2T
(C) 0x71 (113)
(I) 1 to 24
(A) 9
(C) 0x71 (113)
(I) 1 to 24
(A) 3
(C) 0x71 (113)
(I) 1 to 24
(A) 0x13 (19)
RMH
RML
RMS
RMH
RMH
RML
RMS
(C) 0x71 (113)
(I) 1 to 24
(A) 0x12 (18)
Variable O2T
Control Loop
O2T
Alarm O2T
Alarm Set Point High (instance i)
Limit Set Point High (instance i + 1)
Digital State Digital State
Heat Proportional Band (instance i)
Cool Proportional Band (instance i)
Digital State
Bits 16 to 31, Signed 16 bits with implied tenths precision (-3276.8 to 3276.7 )
Control Loop
O2T
Bits 16 to 31, Unsigned 16 bits with implied tenths precision (0 to 6553.5)
Bits 16 to 28, Signed 13 bits whole (-4096 to 4095)
Bits 16 to 28, Signed 13 bits whole (-4096 to 4095)
Bit 29, Clear Latched Input Error (0 = Ignore, 1 = Clear)
Bits 16 to 31, Unsigned 16 bits with implied tenths precision (0 to 6553.5)
Bit 30, Clear Latched Error (0 = Ignore, 1 = Clear)
Bits 16 to 31, This member has paired bits which represent the digital state of up to 8
Variables instance i to instance i + 15 respectively (00 = Off, 01 = On)
Bits 16 to 30, Signed 15 bits with implied tenths precision (-1638.4 to 1638.3 )
Bit 31, Alarm Clear (0 = Ignore, 1 = Clear)
Bits 16 to 31, Signed 16 bits with implied tenths precision (-3276.8 to 3276.7)
Digital State
Compact Class MSW B
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